This application is based upon and claims priority of Japanese Patent Application No. 2001-012418, filed on Jan. 19, 2001, the contents being incorporated herein by reference.
1. Field of the Invention
The present invention relates to plasma display device and methods for controlling the plasma display device. More particularly, the present invention relates to a plasma display device and a method for controlling the plasma display device which are preferably employed for an AC-driven plasma display device having different reference potentials between the drive circuit for driving each of the cells constituting the display portion and the drive control circuit for controlling the drive circuit.
2. Description of the Related Art
Conventionally, AC-driven plasma display panels (PDPs), one of flat display panels, are classified into two-electrode type PDPs which perform selective discharge (address discharge) and sustain discharge using two electrodes and three-electrode type PDPs which perform address discharge using a third electrode. The three-electrode type PDPs are further classified into a type with the third electrode formed on a substrate on which the first and second electrodes for performing sustain discharge are laid out and a type with the third electrode formed on another substrate opposite to the substrate of the first and second electrodes.
All types of the above PDP devices are based on the same operation principle. The arrangement of a PDP device in which the first and second electrodes for performing sustain discharge are formed on the first substrate, and the third electrode is formed on the second substrate opposite to the first substrate will be described below.
FIG. 17 is a view showing the overall arrangement of an AC-driven PDP device. In the AC-driven PDP device 1 shown in FIG. 17, a plurality of cells each corresponding to one pixel of a display image are arrayed in a matrix. FIG. 17 shows an AC-driven PDP device having cells arrayed in a matrix with m rows by n columns. The AC-driven PDP 1 also has scanning electrodes Y1 to Yn and common electrodes X, which are formed to run parallel on the first substrate, and address electrodes A1 to Am which are formed on the second substrate opposite to the first substrate so as to run perpendicular to the electrodes Y1 to Yn and X. The common electrodes X are formed in proximities of the scanning electrodes Y1 to Yn in correspondence with them and commonly connected at terminals on one side.
The common terminal of the common electrodes X is connected to the output terminal of an X-side circuit 2. The scanning electrodes Y1 to Yn are connected to the output terminals of a Y-side circuit 3. The address electrodes A1 to Am are connected to the output terminals of an address-side circuit 4. The X-side circuit 2 is formed from a circuit for repeating discharge. The Y-side circuit 3 is formed from a circuit for executing line-sequential scanning and a circuit for repeating discharge. The address-side circuit 4 is formed from a circuit for selecting a column to be displayed.
The X-side circuit 2, Y-side circuit 3, and address-side circuit 4 are controlled by control signals supplied from a drive control circuit 5. That is, a cell to be turned on is determined by the address-side circuit 4 and the line-sequential scanning circuit in the Y-side circuit 3, and discharge is repeated by the X-side circuit 2 and Y-side circuit 3, thereby performing the display operation of the PDP.
The drive control circuit 5 generates the control signals on the basis of display data D from an external device, a clock CLK indicating the read timing of the display data D, a horizontal sync signal HS, and a vertical sync signal VS and supplies the control signals to the X-side circuit 2, Y-side circuit 3, and address-side circuit 4.
FIG. 18A is a sectional view of a cell Cij as a pixel, which is in the ith row and jth column. Referring to FIG. 18A, the common electrode X and the scanning electrode Yi are formed on a front glass substrate 11. The electrodes X and Yi are coated with a dielectric layer 12 that insulates the electrodes from discharge space 17. The dielectric layer 12 is coated with an MgO (magnesium oxide) protective film 13.
On the other hand, the address electrode Aj is formed on a back glass substrate 14 opposite to the front glass substrate 11. The address electrode Aj is coated with a dielectric layer 15, and the dielectric layer 15 is coated with a phosphor 18. Ne+Xe Penning gas is sealed in the discharge space 17 between the MgO protective film 13 and the dielectric layer 15.
FIG. 18B is a view for explaining the capacitance Cp in the AC-driven PDP. As shown in FIG. 18B, in the AC-driven PDP, capacitive components Ca, Cb, and Cc are present in the discharge space 17, between the common electrode X and the scanning electrode Y, and in the front glass substrate 11, respectively. A capacitance Cpcell per cell is determined by the sum of the capacitive components (Cpcell=Ca+Cb+Cc). The sum of capacitances Cpcell of all the cells in the panel is the panel capacitance Cp.
FIG. 18C is a view for explaining light emission of an AC-driven PDP. As shown in FIG. 18C, striped-shaped red, blue, and green phosphors 18 are laid out and applied to the inner surface of ribs 16. The phosphors 18 are excited by discharge between the common electrode X and the scanning electrode Y so as to emit light.
In addition, a method for driving an AC-driven PDP has been suggested. The method employs a drive circuit as shown in FIG. 19 to apply a positive potential to one electrode and a negative potential to the other electrode, thereby making use of a potential difference between the electrodes to perform discharge therebetween.
FIG. 19 is a circuit diagram showing the arrangement of a drive circuit for an AC-driven PDP.
Referring to FIG. 19, a capacitive load 20 (hereinafter referred to as a xe2x80x9cloadxe2x80x9d) is the total capacitance of the cells formed between one common electrode X and one scanning electrode Y. The common electrode X and the scanning electrode Y are formed on the load 20. Here, the scanning electrode Y is a given scanning electrode of the scanning electrodes Y1 to Yn.
On the common electrode X side, switches SW1 and SW2 are connected in series between the ground (GND) and a power supply line for a potential (Vs/2) supplied from a power supply (not shown). One terminal of a capacitor C1 is connected to an interconnection node between the two switches SW1 and SW2, while a switch SW3 is connected between the other terminal of the capacitor C1 and the GND.
Switches SW4 and SW5 are connected in series between the two terminals of the capacitor C1. An interconnection node between the two switches SW4 and SW5 is connected on the way to the common electrode X of the load 20 via an output line OUTC and to a power recovery circuit 21 as well. Furthermore, a switch SW6 having a resistor R1 is connected between a second signal line OUTB and a power supply line for generating a write potential Vw.
The power recovery circuit 21 has two coils L1 and L2 connected to the load 20, a diode D2 and a transistor Tr1 that are connected in series to the coil L1, and a diode D3 and a transistor Tr2 that are connected in series to the coil L2. The power recovery circuit 21 also has a capacitor C2 to be connected between the interconnection node of the two transistors Tr1 and Tr2 and the second signal line OUTB.
Thus, the load 20 and the coils L1 and L2 each connected thereto constitute two resonant circuits. That is, the power recovery circuit 21 is provided with two L-C resonant circuits in which charges supplied to the panel by the resonance of the coil L1 and the load 20 are recovered through the resonance of the coil L2 and the load 20.
On the scanning electrode Y side, switches SW1xe2x80x2 and SW2xe2x80x2 are connected in series between the ground (GND) and a power supply line for a potential (Vs/2) supplied from a power supply (not shown). One terminal of a capacitor C4 is connected to an interconnection node of the two switches SW1xe2x80x2 and SW2xe2x80x2, while a switch SW3xe2x80x2 is connected between the other terminal of the capacitor C4 and the GND.
Switch SW4xe2x80x2 connected to the one terminal of the capacitor C4 is connected to the cathode of the diode D7, and the anode of the diode D7 is connected to the other terminal of the capacitor C4. Switch SW5xe2x80x2 connected to the other terminal of the capacitor C4 is connected to the anode of the diode D6, and the cathode of the diode D6 is connected to the one terminal of the capacitor C4.
Moreover, one terminal of the switch SW4xe2x80x2 connected to the cathode of the diode D7 and one terminal of the switch SW5xe2x80x2 connected to the anode of the diode D6 are connected with the load 20 via a scan driver 22 and a power recovery circuit 21xe2x80x2 as well. Furthermore, a switch SW6xe2x80x2 having a resistor R1xe2x80x2 is connected between a fourth signal line OUTBxe2x80x2 and the power supply line for generating a write potential Vw.
The power recovery circuit 21xe2x80x2 has two coils L3 and L4 connected to the load 20 via the scan driver 22, a diode D4 and a transistor Tr3 that are connected in series to the coil L3, and a diode D5 and a transistor Tr4 that are connected in series to the coil L4. The power recovery circuit 21xe2x80x2 also has a capacitor C3 to be connected between the common terminal of the two transistors Tr3 and Tr4 and the fourth signal line OUTBxe2x80x2.
The power recovery circuit 21xe2x80x2 is also provided with two L-C resonant circuits in which charges supplied to the load 20 by the resonance of the coil L4 and the load 20 are recovered through the resonance of the coil L3 and the load 20.
In addition to the configuration, there are also provided three transistors Tr5, Tr6, and Tr7 and two diodes D6 and D7 on the scanning electrode Y side. When turned on, the transistor Tr5 allows a resistor R2 connected thereto to act to blunt the waveform of a pulse potential applied to the scanning electrode Y. The transistor Tr5 and the resistor R2 are connected in parallel to the switch SW5xe2x80x2.
The transistors Tr6 and Tr7 are adapted to provide a potential difference (Vs/2) across the scan driver 22 in an address period, which is described later. That is, in the address period, the switch SW2xe2x80x2 and the transistor Tr6 are turned on, thereby causing the potential at the upper side of the scan driver 22 to reach the ground level. Moreover, the transistor Tr7 is turned on to thereby cause the negative potential (xe2x88x92Vs/2) outputted to the fourth signal line OUTBxe2x80x2 in accordance with the charges accumulated in the capacitor C4 to be applied to the lower side of the scan driver 22. Upon outputting a scan pulse, this makes it possible to allow the scan driver 22 to apply the negative potential (xe2x88x92Vs/2) to the scanning electrode Y.
The switches SW1 to SW6, SW1xe2x80x2 to Sw6xe2x80x2 and the transistors Tr1 to Tr7 are controlled by control signals supplied from a drive control circuit 31. The drive control circuit 31 comprises logic circuits, and generates the control signals on the basis of display data D from an external device, a clock CLK, a horizontal sync signal HS, and a vertical sync signal VS to then supply the control signals to the switches SW1 to SW6, SW1xe2x80x2 to Sw6xe2x80x2 and the transistors Tr1 to Tr7.
Incidentally, FIG. 19 shows control lines connected the drive control circuit 31 with the switches SW4, SW5, SW4xe2x80x2, and SW5xe2x80x2 and the transistors Tr1 to Tr4. However, there also exist control lines that connect the drive control circuit 31 with the switches SW1 to SW6, SW1xe2x80x2 to SW6xe2x80x2 and the transistors Tr1 to Tr7.
FIG. 20 is a timing chart showing drive waveforms provided by the drive circuit for the AC-driven PDP configured as shown in FIG. 19. FIG. 20 shows one of a plurality of subfields of one frame. One subfield is divided into a reset period comprised of a full write period and a full erase period, an address period, and a sustain discharge period.
In FIG. 20, in the reset period, first, on the common electrode X side, the switches SW2 and SW5 are turned on and the switches SW1, SW3, SW4, and SW6 are turned off. This causes the potential of the second signal line OUTB to be reduced down to (xe2x88x92Vs/2) in accordance with the charges accumulated in the capacitor C1. Then, the potential (xe2x88x92Vs/2) is output to the output line OUTC through the switch SW5 and then applied to the common electrode X of the load 20.
On the scanning electrode Y side, the switches SW1xe2x80x2, SW4xe2x80x2, and SW6xe2x80x2 are turned on and the switches SW2xe2x80x2, SW3xe2x80x2, and SW5xe2x80x2 are turned off. This causes the potential Vw added by a potential (Vs/2) resulting from the charges accumulated in the capacitor C4 to be applied to the output line OUTCxe2x80x2. Then, the potential (Vs/2+Vw) is applied to the scanning electrode Y of the load 20. At this time, the resistor R1xe2x80x2 in the switch SW6xe2x80x2 acts to gradually increase the potential with the passage of time.
This causes the potential difference between the common electrode X and the scanning electrode Y to reach (Vs+Vw), and discharge to be performed in all cells of all display lines independently of the preceding display state, thereby forming wall charges (full writing).
Then, each switch is controlled as appropriate to bring the potential of the common electrode X and the scanning electrode Y back to the ground level, and then a state opposite to the state is created on the common electrode X and the scanning electrode Y. That is, on the common electrode X side, the switches SW1, SW4, and SW6 are turned on, and the switches SW2, SW3, and SW5 are turned off, while on the scanning electrode Y side, the switches SW2xe2x80x2 and SW5xe2x80x2 are turned on, and the switches SW1xe2x80x2, SW3xe2x80x2, SW4xe2x80x2, and SW6xe2x80x2 are turned off.
This allows the potential applied to the common electrode X to increase continuously from the ground level up to (Vs/2+Vw) with the passage of time, while the potential applied to the scanning electrode Y drops down to (xe2x88x92Vs/2). This causes the potential of wall charges themselves to exceed the discharge start potential in all the cells, thereby starting discharge. At this time, as described above, by allowing the potential applied to the common electrode X to continuously increase as time goes by, weak discharge is performed to erase the accumulated wall charges excluding a part thereof (full erasing).
Then, in the address period, address discharge is line-sequentially performed to turn on/off each cell in accordance with the display data. At this time, on the common electrode X side, the switches SW1, SW3, and SW4 are turned on, and the switches SW2, SW5, and SW6 are turned off. The potential of the first signal line OUTA is thereby raised up to the potential (Vs/2) that is provided via the switch SW1. Then, the potential (Vs/2) is outputted to the output line OUTC through the switch SW4 and applied to the common electrode X of the load 20.
In addition, upon the application of a potential to a scanning electrode Y corresponding to a given display line, the switch SW2xe2x80x2 and the transistor Tr6 are turned on, thereby causing the potential at the upper side of the scan driver 22 to be brought down to the ground level. Moreover, the transistor Tr7 is turned on, thereby causing the negative potential (xe2x88x92Vs/2) outputted to the fourth signal line OUTBxe2x80x2 in accordance with the charges accumulated in the capacitor C4 to be applied to the lower side of the scan driver 22. Accordingly, a potential level of (xe2x88x92Vs/2) is applied to the scanning electrodes Y selected line-sequentially, while the ground level potential is applied to non-selected scanning electrodes Y of the load 20.
At this time, an address pulse having a potential Va is selectively applied to the address electrode Aj in the address electrode A1 to Am, which corresponds to a cell which should cause sustain discharge, i.e., a cell to be turned on. As a result, discharge occurs between the address electrode Aj of the cell to be turned on and the line-sequentially selected scanning electrode Y. With this priming (pilot flame), discharge between the common electrode X and the scanning electrode Y immediately starts. Wall charges in an amount enough for the next sustain discharge are accumulated on the MgO protective film on the common electrode X and scanning electrode Y of the selected cell.
Then, in the sustaining discharge period, the two switches SW1 and SW3 are first turned on, and the remaining switches SW2, and SW4 to SW6 are turned off on the common electrode X side. At this time, the potential of the first signal line OUTA reaches (+Vs/2) and the second signal line OUTB reaches the ground level. Here, the transistor Tr1 in the power recovery circuit 21 is turned on to thereby allow the coil L1 and the capacitance of the load 20 to produce L-C resonance, and the charges that have been recovered in the capacitor C2 is supplied to the load 20 through the transistor Tr1, the diode D2, and the coil L1.
At this time, on the scanning electrode Y side, the switch SW2xe2x80x2 has been turned on. Accordingly, the current supplied from the capacitor C2 to the common electrode X via the switch SW3 on the common electrode X side passes through the diode in the scan driver 22 on the scanning electrode Y side and the diode D6 to be supplied to the GND via the third signal line OUTAxe2x80x2 and the switch SW2xe2x80x2. The current flowing as described above causes the potential of the common electrode X to increase gradually as shown in FIG. 20. Then, the switch SW4 is turned on near the peak potential produced upon the resonance, thereby the potential of the common electrode X is clamped to the potential (Vs/2).
Subsequently, on the scanning electrode Y side, the transistor Tr3 in the power recovery circuit 21xe2x80x2 is further turned on. This allows the coil L3 and the capacitance of the load 20 to produce L-C resonance. A current is supplied to the common electrode X from the switch SW3 and the capacitor C1 on the common electrode X side through the first signal line OUTA, and the switch SW4. The current passes through the diode in the scan driver 22 on the scanning electrode Y side and the diode D4 in the power recovery circuit 21xe2x80x2 and is then supplied to the GND via the transistor Tr3, the capacitor C3, the capacitor C4, and the switch SW2xe2x80x2. The current flowing as described above causes the potential of the scanning electrode Y to decrease gradually as shown in FIG. 20. At this time, part of the charges can be recovered in the capacitor C3. Then, the switch SW5xe2x80x2 is also turned on near the peak potential produced upon the resonance, whereby the potential of the scanning electrode Y is clamped to the potential (xe2x88x92Vs/2).
Similarly, to change the potential applied to the common electrode X and the scanning electrode Y from the potential (xe2x88x92Vs/2) to the ground level (0V), the charges that have been recovered in the capacitors C2 and C3 in the power recovery circuits 21 and 21xe2x80x2 is supplied, thereby allowing the applied potential to gradually increase.
In addition, to change the potential applied to the common electrode X and the scanning electrode Y from the potential (Vs/2) to the ground level (0V), the charges that have been accumulated in the load 20 is supplied to the GND, thereby allowing the applied potential to gradual
ly decrease and a part of the charges that have been accumulated in the load 20 to be recovered in the capacitors C2 and C3 in the power recovery circuits 21 and 21xe2x80x2.
As described above, in the sustain discharge period, potentials (+Vs/2 and xe2x88x92Vs/2) different in polarity from each other are applied alternately to the common electrode X and the scanning electrode Y of each display line to perform sustain discharge to thereby display one subfield of image.
In the drive circuit for the AC-driven PDP, the drive control circuit 31 comprised logic circuits or the like employs the GND level as a reference potential. However, during the drive operation, the reference potential of output elements varies to which control signals are supplied from the drive control circuit 31 and by which potentials are supplied to the common electrode X and the scanning electrode Y. Here, meant by the output elements are the switches SW4, SW5, SW4xe2x80x2, and SW5xe2x80x2, and the transistors Tr1 to Tr4 in the power recovery circuits 21 and 21xe2x80x2. For this reason, a variation in potential of the output elements could produce backflow of power to the drive control circuit 31, thereby causing a high potential to be applied to the drive control circuit 31, for example, upon supplying the signal generated by the drive control circuit 31 to the output elements.
As a method for solving this problem, such a method can be contemplated in which components having a high breakdown potential are employed as the elements in the output portion of the drive control circuit 31 to thereby prevent the effects caused by the variations in potential of the output elements. However, there was a problem that the output portion of the drive control circuit 31 configured using components having a high breakdown potential made the circuit complicated.
Furthermore, in the drive circuit for the AC-driven PDP, suppose that the power recovery circuits 21 and 21xe2x80x2 work improperly, that is, potentials across the capacitors C2 and C3 deviate from normal potentials. In this case, output loss would become greater in the drive operation of the drive circuit to cause each of the elements constituting the drive circuit to generate a greater amount of heat, thereby leading to damage to the elements in some cases.
The present invention was developed to solve such a problem. It is therefore an object of the present invention to provide a highly reliable plasma display device without employing components or the like having a high breakdown potential.
In addition, it is a second object of the present invention to make it possible to prevent damage to the elements when the power recovery circuit works improperly.
The plasma display device according to an aspect of the present invention is characterized by comprising a signal transfer circuit. The signal transfer circuit converts a control signal, for controlling an output element for supplying a potential to an electrode provided for applying a potential to a display cell and producing discharge therein, to a signal having a reference potential of the output element and then supplies the resulting signal to the output element.
The plasma display device according to another aspect of the present invention is characterized by lowering a power supply potential for driving the plasma display device when a power recovery potential detected by the potential detector circuit for detecting the power recovery potential of a power recovery circuit is different from a power recovery potential indicative of the properly operating power recovery circuit.
According to the present invention configured as described above, a control signal for controlling an output element for supplying a potential to an electrode is converted to a signal having the reference potential of the output element and the resulting signal is then supplied to the output element. This makes it possible to transfer the control signal, with the reference potential being isolated. Accordingly, the side for supplying the control signal could be prevented from being affected by variations in potential of the output element or the like.
Furthermore, according to anther aspect of the present invention, the power recovery potential of the power recovery circuit is detected. When the power recovery potential detected is different from a power recovery potential indicative of the properly operating power recovery circuit, the power supply potential for driving the plasma display device is lowered. This makes it possible to stop the operation of the plasma display device before the occurrence of damage to the elements.